For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
The further reduction in scale of integrated circuit devices has called for the increased usage of non-planar transistors such as tri-gate transistors, FinFETs, TFETS, omega-FETs, and double-gate transistors. Despite improved performance, drive capability of tri-gate transistors are conventionally sized by the integer number of fins which are placed under the controlling gate. Such a limitation in scalability of tri-gate transistors results in usage of unnecessary larger transistors and increase in power consumption. Therefore, there exists a need for a semiconductor structure and a manufacturing process that enhances the scalability of the tri-gate transistors.